1:[1] (1) real: [] line: [; CHARGER.CONF V0.02 ] 1:[1] (2) real: [ ] line: [ ] 1:[1] (3) real: [] line: [; This configuration file acts both as a basic setup of ] 1:[1] (4) real: [] line: [; the BatMods and the documentation for itself ] 1:[1] (5) real: [] line: [; comments start with ';' ] 1:[1] (6) real: [] line: [; ] 1:[1] (7) real: [] line: [; A array is denoted by a .1 - .(maxindex) ] 1:[1] (8) real: [] line: [; ] 1:[1] (9) real: [] line: [; NOTE THAT THIS IS BETA CODE! ] 1:[1] (10) real: [] line: [; USE AT YOUR OWN RISK! ] 1:[1] (11) real: [ ] line: [ ] 1:[1] (12) real: [ ] line: [ ] 1:[1] (13) real: [PWM_SEED=100 ] line: [PWM_SEED=100 ; sets the value the PWM will start out at ] 1:[1] (13) token: [PWM_SEED] value: [100] 1:[8] (13): PWM_SEED=100 write 100 @ 8178 1:[1] (14) real: [ ] line: [ ; when charging enables ] 1:[1] (15) real: [ ] line: [ ] 1:[1] (16) real: [MY_NET_ADDR=1 ] line: [MY_NET_ADDR=1 ; sets the network address of this charger ] 1:[1] (16) token: [MY_NET_ADDR] value: [1] 1:[8] (16): MY_NET_ADDR=1 write 1 @ 8191 1:[1] (17) real: [ ] line: [ ; LEAVE THIS AT ONE - SEE THE EMAIL THIS FILE CAME WITH! ] 1:[1] (18) real: [ ] line: [ ] 1:[1] (19) real: [LAST_ERROR=0 ] line: [LAST_ERROR=0 ; resets the last error storage byte ] 1:[1] (19) token: [LAST_ERROR] value: [0] 1:[8] (19): LAST_ERROR=0 write 0 @ 8190 1:[1] (20) real: [LAST_MESSAGE_SIZE=0 ] line: [LAST_MESSAGE_SIZE=0 ; resets the last message size debug counter ] 1:[1] (20) token: [LAST_MESSAGE_SIZE] value: [0] 1:[8] (20): LAST_MESSAGE_SIZE=0 write 0 @ 8189 1:[1] (21) real: [NUM_SAMPLES=10 ] line: [NUM_SAMPLES=10 ; sets the number of samples to take on a poll() event ] 1:[1] (21) token: [NUM_SAMPLES] value: [10] 1:[8] (21): NUM_SAMPLES=10 write 10 @ 8188 1:[1] (22) real: [ ] line: [ ; beware - too high a number here and the charger ] 1:[1] (23) real: [ ] line: [ ; will be too busy polling to do anything useful, ] 1:[1] (24) real: [ ] line: [ ] 1:[1] (25) real: [NUM_VF=10 ] line: [NUM_VF=10 ; sets the number of voltage-to-frequecy (hv) samples ] 1:[1] (25) token: [NUM_VF] value: [10] 1:[8] (25): NUM_VF=10 write 10 @ 8187 1:[1] (26) real: [ ] line: [ ; see warning on NUM_SAMPLES ] 1:[1] (27) real: [ ] line: [ ] 1:[1] (28) real: [DLY_VF=4 ] line: [DLY_VF=4 ; sets the number of ticks to count() for when ] 1:[1] (28) token: [DLY_VF] value: [4] 1:[8] (28): DLY_VF=4 write 4 @ 8186 1:[1] (29) real: [ ] line: [ ; sampling the voltage to frequency converter ] 1:[1] (30) real: [ ] line: [ ; beware, this number affects hv calibration ] 1:[1] (31) real: [ ] line: [ ; if you change it, you must rerun calibrate_hv ] 1:[1] (32) real: [ ] line: [ ] 1:[1] (33) real: [DIV_VF=1 ] line: [DIV_VF=1 ; sets the number the output of count() is divided by ] 1:[1] (33) token: [DIV_VF] value: [1] 1:[8] (33): DIV_VF=1 write 1 @ 8185 1:[1] (34) real: [ ] line: [ ; beware: setting it to zero may make bad things happen ] 1:[1] (35) real: [ ] line: [ ; see also the warnings on DLY_VF ] 1:[1] (36) real: [ ] line: [ ] 1:[1] (37) real: [ ] line: [ ] 1:[1] (38) real: [DL_LOCK=0 ] line: [DL_LOCK=0 ; I don't know what it's for either ] 1:[1] (38) token: [DL_LOCK] value: [0] 1:[8] (38): DL_LOCK=0 write 0 @ 8184 1:[1] (39) real: [ ] line: [ ; it's defined in the code and then never used ] 1:[1] (40) real: [ ] line: [ ; but I'm too lazy to go remove it ] 1:[1] (41) real: [ ] line: [ ] 1:[1] (42) real: [ ] line: [ ; maybe we'll use it later? ] 1:[1] (43) real: [ ] line: [ ; for the bootloader or something? ] 1:[1] (44) real: [ ] line: [ ] 1:[1] (45) real: [PWM_FREQ=5000 ] line: [PWM_FREQ=5000 ; sets the frequency the PWM outputs to throttle the BatMod ] 1:[1] (45) token: [PWM_FREQ] value: [5000] 1:[8] (45): PWM_FREQ=5000 write 5000 @ 8182 1:[1] (46) real: [ ] line: [ ; please use a little common sense here ] 1:[1] (47) real: [ ] line: [ ] 1:[1] (48) real: [PWM_OFFSET=140 ] line: [PWM_OFFSET=140 ; sets the turn-on threshhold of the PWM ] 1:[1] (48) token: [PWM_OFFSET] value: [140] 1:[8] (48): PWM_OFFSET=140 write 140 @ 8181 1:[1] (49) real: [ ] line: [ ; increase this number (and ajust PWM_SEED accordingly) ] 1:[1] (50) real: [ ] line: [ ; if your BatMod won't make enough volts ] 1:[1] (51) real: [ ] line: [ ] 1:[1] (52) real: [AVG_NUM=50 ] line: [AVG_NUM=50 ; controls the number of samples to keep in the running avg ] 1:[1] (52) token: [AVG_NUM] value: [50] 1:[8] (52): AVG_NUM=50 write 50 @ 8180 1:[1] (53) real: [ ] line: [ ; note that if this is the same or less than NUM_SAMPLES ] 1:[1] (54) real: [ ] line: [ ; the effect is that the only sensor results that ] 1:[1] (55) real: [ ] line: [ ; are reflected are the most recent ones ] 1:[1] (56) real: [ ] line: [ ; ] 1:[1] (57) real: [ ] line: [ ; contrawise, if this number is too big ] 1:[1] (58) real: [ ] line: [ ; it will take a long time for the charger ] 1:[1] (59) real: [ ] line: [ ; to react to anything ] 1:[1] (60) real: [ ] line: [ ] 1:[1] (61) real: [CONFIG_LOCKED=69] line: [CONFIG_LOCKED=69; the software lock ] 1:[1] (61) token: [CONFIG_LOCKED] value: [69] 1:[8] (61): CONFIG_LOCKED=69 write 69 @ 8179 1:[1] (62) real: [ ] line: [ ; this has the following magic values: ] 1:[1] (63) real: [ ] line: [ ] 1:[1] (64) real: [ ] line: [ ; 55 = allow writing a block to eeprom for uploading bootloader ] 1:[1] (65) real: [ ] line: [ ; 121 = allow executing a bootloader ] 1:[1] (66) real: [ ] line: [ ; 42 = allow manual commanding of PWM levels ] 1:[1] (67) real: [ ] line: [ ; 69 = normal operation ] 1:[1] (68) real: [ ] line: [ ; ] 1:[1] (69) real: [ ] line: [ ; any value besides 69 will result in some of the config ] 1:[1] (70) real: [ ] line: [ ; options being reset to default levels ] 1:[1] (71) real: [ ] line: [ ; whenever the board reboots ] 1:[1] (72) real: [LAST_ERRNO.1=0 ] line: [LAST_ERRNO.1=0 ] 1:[1] (72) token: [LAST_ERRNO.1] value: [0] 1:[2] (72) token: [LAST_ERRNO] array slice: [1] 1:[8] (72): LAST_ERRNO=0 write 0 @ 8176 1:[1] (73) real: [LAST_ERRNO.2=0 ] line: [LAST_ERRNO.2=0 ; this array contains the last two reported errors ] 1:[1] (73) token: [LAST_ERRNO.2] value: [0] 1:[2] (73) token: [LAST_ERRNO] array slice: [2] 1:[8] (73): LAST_ERRNO=0 write 0 @ 8177 1:[1] (74) real: [ ] line: [ ] 1:[1] (75) real: [MAX_WATTS=200 ] line: [MAX_WATTS=200 ; this sets the most watts the charger will ever make ] 1:[1] (75) token: [MAX_WATTS] value: [200] 1:[8] (75): MAX_WATTS=200 write 200 @ 8160 1:[1] (76) real: [MAX_VOLTS=17.00 ] line: [MAX_VOLTS=17.00 ; this sets the most volts teh charger will ever make ] 1:[1] (76) token: [MAX_VOLTS] value: [17.00] 1:[8] (76): MAX_VOLTS=17.00 write 237 @ 8162 1:[1] (77) real: [MAX_AMPS=15.00 ] line: [MAX_AMPS=15.00 ; this sets the most amps the charger will ever make ] 1:[1] (77) token: [MAX_AMPS] value: [15.00] 1:[8] (77): MAX_AMPS=15.00 write 150 @ 8163 1:[1] (78) real: [MAX_CHG_TEMP=1 ] line: [MAX_CHG_TEMP=1 ; this number is backwards ] 1:[1] (78) token: [MAX_CHG_TEMP] value: [1] 1:[8] (78): MAX_CHG_TEMP=1 write 1 @ 8164 1:[1] (79) real: [ ] line: [ ; meaning whenever the charger sensor falls below this level ] 1:[1] (80) real: [ ] line: [ ; charging will be terminated ] 1:[1] (81) real: [ ] line: [ ; suggested default is 45 ] 1:[1] (82) real: [ ] line: [ ] 1:[1] (83) real: [MAX_BATT_TEMP=120 ] line: [MAX_BATT_TEMP=120 ] 1:[1] (83) token: [MAX_BATT_TEMP] value: [120] 1:[8] (83): MAX_BATT_TEMP=120 write 160 @ 8165 1:[1] (84) real: [ ] line: [ ] 1:[1] (85) real: [PHASES_ENABLED=5 ] line: [PHASES_ENABLED=5 ; this number is a mask ] 1:[1] (85) token: [PHASES_ENABLED] value: [5] 1:[8] (85): PHASES_ENABLED=5 write 5 @ 8166 1:[1] (86) real: [ ] line: [ ;so ] 1:[1] (87) real: [ ] line: [ ; 1 = ? ] 1:[1] (88) real: [ ] line: [ ; 2 = phase 1 enabled ] 1:[1] (89) real: [ ] line: [ ; 4 = phase 2 enabled ] 1:[1] (90) real: [ ] line: [ ; 8 = phase 3 enabled ] 1:[1] (91) real: [ ] line: [ ; 16 = phase 4 enabled ] 1:[1] (92) real: [ ] line: [ ; 32 = phase 5 enabled ] 1:[1] (93) real: [ ] line: [ ; 64 = phase 6 enabled ] 1:[1] (94) real: [ ] line: [ ; 128 = phase 7 enabled ] 1:[1] (95) real: [ ] line: [ ] 1:[1] (96) real: [ ] line: [ ; add 'em togeather to get the mask you want ] 1:[1] (97) real: [ ] line: [ ] 1:[1] (98) real: [SCALE_BACK_CHG_TEMP=49 ] line: [SCALE_BACK_CHG_TEMP=49 ; see MAX_CHG_TEMP - when the sensor reports below this ] 1:[1] (98) token: [SCALE_BACK_CHG_TEMP] value: [49] 1:[8] (98): SCALE_BACK_CHG_TEMP=49 write 49 @ 8167 1:[1] (99) real: [ ] line: [ ; number (but above MAX_CHG_TEMP) the charger will ] 1:[1] (100) real: [ ] line: [ ; throttle back ] 1:[1] (101) real: [ ] line: [ ] 1:[1] (102) real: [CHARGE_INHIBIT_ERRNO_MASK=0 ] line: [CHARGE_INHIBIT_ERRNO_MASK=0 ] 1:[1] (102) token: [CHARGE_INHIBIT_ERRNO_MASK] value: [0] 1:[8] (102): CHARGE_INHIBIT_ERRNO_MASK=0 write 0 @ 8168 1:[1] (103) real: [ ] line: [ ; this value is a mask ] 1:[1] (104) real: [ ] line: [ ; the following errors are defined ] 1:[1] (105) real: [ ] line: [ ; 1 = charger too hot ] 1:[1] (106) real: [ ] line: [ ; 2 = charger too cold (or sensor failed) ] 1:[1] (107) real: [ ] line: [ ; 4 = uncommanded charging ] 1:[1] (108) real: [ ] line: [ ; 8 = battery over voltage (MAX_VOLTS) ] 1:[1] (109) real: [ ] line: [ ; 16 = battery under voltage (MIN_VOLTS) ] 1:[1] (110) real: [ ] line: [ ; 32 = battery over temp (MAX_TEMP) ] 1:[1] (111) real: [ ] line: [ ; 64 = battery under temp (MIN_TEMP) ] 1:[1] (112) real: [ ] line: [ ; 128 = VESTA board has crashed and rebooted ] 1:[1] (113) real: [ ] line: [ ; ] 1:[1] (114) real: [ ] line: [ ; any errno that matches this mask will inhibit ] 1:[1] (115) real: [ ] line: [ ; charging. Because you have no way to communicate ] 1:[1] (116) real: [ ] line: [ ; with the network right now, set this value to zero ] 1:[1] (117) real: [ ] line: [ ] 1:[1] (118) real: [TIMEOUT_MINUTES=60 ] line: [TIMEOUT_MINUTES=60 ] 1:[1] (118) token: [TIMEOUT_MINUTES] value: [60] 1:[8] (118): TIMEOUT_MINUTES=60 write 60 @ 8169 1:[1] (119) real: [ ] line: [ ; when the VESTA board has been idle for this ] 1:[1] (120) real: [ ] line: [ ; many minutes, it will go to sleep ] 1:[1] (121) real: [ ] line: [ ] 1:[1] (122) real: [ ] line: [ ; note that a sleeping board ] 1:[1] (123) real: [ ] line: [ ; can not process a network event immediately ] 1:[1] (124) real: [ ] line: [ ; or report undervolts and the like ] 1:[1] (125) real: [ ] line: [ ] 1:[1] (126) real: [SLEEP_SECONDS=60 ] line: [SLEEP_SECONDS=60 ] 1:[1] (126) token: [SLEEP_SECONDS] value: [60] 1:[8] (126): SLEEP_SECONDS=60 write 60 @ 8170 1:[1] (127) real: [ ] line: [ ; when a VESTA board has been idle for TIMEOUT_MINUTES ] 1:[1] (128) real: [ ] line: [ ; it will go to sleep ] 1:[1] (129) real: [ ] line: [ ] 1:[1] (130) real: [PHASE_CHARGE_VOLTS.1=14.70 ] line: [PHASE_CHARGE_VOLTS.1=14.70 ] 1:[1] (130) token: [PHASE_CHARGE_VOLTS.1] value: [14.70] 1:[2] (130) token: [PHASE_CHARGE_VOLTS] array slice: [1] 1:[8] (130): PHASE_CHARGE_VOLTS=14.70 write 191 @ 7936 1:[1] (131) real: [PHASE_CHARGE_VOLTS.2=16.80 ] line: [PHASE_CHARGE_VOLTS.2=16.80 ] 1:[1] (131) token: [PHASE_CHARGE_VOLTS.2] value: [16.80] 1:[2] (131) token: [PHASE_CHARGE_VOLTS] array slice: [2] 1:[8] (131): PHASE_CHARGE_VOLTS=16.80 write 233 @ 7937 1:[1] (132) real: [PHASE_CHARGE_VOLTS.3=14.00 ] line: [PHASE_CHARGE_VOLTS.3=14.00 ; for each phase, sets a constant voltage limit ] 1:[1] (132) token: [PHASE_CHARGE_VOLTS.3] value: [14.00] 1:[2] (132) token: [PHASE_CHARGE_VOLTS] array slice: [3] 1:[8] (132): PHASE_CHARGE_VOLTS=14.00 write 177 @ 7938 1:[1] (133) real: [PHASE_CHARGE_VOLTS.4=14.00 ] line: [PHASE_CHARGE_VOLTS.4=14.00 ] 1:[1] (133) token: [PHASE_CHARGE_VOLTS.4] value: [14.00] 1:[2] (133) token: [PHASE_CHARGE_VOLTS] array slice: [4] 1:[8] (133): PHASE_CHARGE_VOLTS=14.00 write 177 @ 7939 1:[1] (134) real: [PHASE_CHARGE_VOLTS.5=14.00 ] line: [PHASE_CHARGE_VOLTS.5=14.00 ] 1:[1] (134) token: [PHASE_CHARGE_VOLTS.5] value: [14.00] 1:[2] (134) token: [PHASE_CHARGE_VOLTS] array slice: [5] 1:[8] (134): PHASE_CHARGE_VOLTS=14.00 write 177 @ 7940 1:[1] (135) real: [PHASE_CHARGE_VOLTS.6=14.00 ] line: [PHASE_CHARGE_VOLTS.6=14.00 ] 1:[1] (135) token: [PHASE_CHARGE_VOLTS.6] value: [14.00] 1:[2] (135) token: [PHASE_CHARGE_VOLTS] array slice: [6] 1:[8] (135): PHASE_CHARGE_VOLTS=14.00 write 177 @ 7941 1:[1] (136) real: [PHASE_CHARGE_VOLTS.7=14.00 ] line: [PHASE_CHARGE_VOLTS.7=14.00 ] 1:[1] (136) token: [PHASE_CHARGE_VOLTS.7] value: [14.00] 1:[2] (136) token: [PHASE_CHARGE_VOLTS] array slice: [7] 1:[8] (136): PHASE_CHARGE_VOLTS=14.00 write 177 @ 7942 1:[1] (137) real: [ ] line: [ ] 1:[1] (138) real: [PHASE_CHARGE_AMPS.1=10.00 ] line: [PHASE_CHARGE_AMPS.1=10.00 ] 1:[1] (138) token: [PHASE_CHARGE_AMPS.1] value: [10.00] 1:[2] (138) token: [PHASE_CHARGE_AMPS] array slice: [1] 1:[8] (138): PHASE_CHARGE_AMPS=10.00 write 100 @ 7944 1:[1] (139) real: [PHASE_CHARGE_AMPS.2=2.00 ] line: [PHASE_CHARGE_AMPS.2=2.00 ] 1:[1] (139) token: [PHASE_CHARGE_AMPS.2] value: [2.00] 1:[2] (139) token: [PHASE_CHARGE_AMPS] array slice: [2] 1:[8] (139): PHASE_CHARGE_AMPS=2.00 write 20 @ 7945 1:[1] (140) real: [PHASE_CHARGE_AMPS.3=2.5 ] line: [PHASE_CHARGE_AMPS.3=2.5 ; for each phase, sets a constant current limit ] 1:[1] (140) token: [PHASE_CHARGE_AMPS.3] value: [2.5] 1:[2] (140) token: [PHASE_CHARGE_AMPS] array slice: [3] 1:[8] (140): PHASE_CHARGE_AMPS=2.5 write 25 @ 7946 1:[1] (141) real: [PHASE_CHARGE_AMPS.4=0 ] line: [PHASE_CHARGE_AMPS.4=0 ] 1:[1] (141) token: [PHASE_CHARGE_AMPS.4] value: [0] 1:[2] (141) token: [PHASE_CHARGE_AMPS] array slice: [4] 1:[8] (141): PHASE_CHARGE_AMPS=0 write 0 @ 7947 1:[1] (142) real: [PHASE_CHARGE_AMPS.5=0 ] line: [PHASE_CHARGE_AMPS.5=0 ] 1:[1] (142) token: [PHASE_CHARGE_AMPS.5] value: [0] 1:[2] (142) token: [PHASE_CHARGE_AMPS] array slice: [5] 1:[8] (142): PHASE_CHARGE_AMPS=0 write 0 @ 7948 1:[1] (143) real: [PHASE_CHARGE_AMPS.6=0 ] line: [PHASE_CHARGE_AMPS.6=0 ] 1:[1] (143) token: [PHASE_CHARGE_AMPS.6] value: [0] 1:[2] (143) token: [PHASE_CHARGE_AMPS] array slice: [6] 1:[8] (143): PHASE_CHARGE_AMPS=0 write 0 @ 7949 1:[1] (144) real: [PHASE_CHARGE_AMPS.7=0 ] line: [PHASE_CHARGE_AMPS.7=0 ] 1:[1] (144) token: [PHASE_CHARGE_AMPS.7] value: [0] 1:[2] (144) token: [PHASE_CHARGE_AMPS] array slice: [7] 1:[8] (144): PHASE_CHARGE_AMPS=0 write 0 @ 7950 1:[1] (145) real: [ ] line: [ ] 1:[1] (146) real: [] line: [; ignore these lines and use the parsed version below for easier setting ] 1:[1] (147) real: [] line: [; of time ] 1:[1] (148) real: [ ] line: [ ] 1:[1] (149) real: [] line: [;PHASE_CHARGE_TIME_LO.0=15 ; low order byte, seconds (this is half a hour) ] 1:[1] (150) real: [] line: [;PHASE_CHARGE_TIME_LO.1=16 ; low order byte, seconds ] 1:[1] (151) real: [] line: [;PHASE_CHARGE_TIME_LO.2=15 ; low order byte, seconds ] 1:[1] (152) real: [ ] line: [ ] 1:[1] (153) real: [] line: [;PHASE_CHARGE_TIME_HI.0=7 ; high order byte, seconds (this is half a hour)) ] 1:[1] (154) real: [] line: [;PHASE_CHARGE_TIME_HI.1=15 ; high order byte, seconds (this is a hour)) ] 1:[1] (155) real: [] line: [;PHASE_CHARGE_TIME_HI.2=7 ; high order byte, seconds (this is half a hour)) ] 1:[1] (156) real: [ ] line: [ ] 1:[1] (157) real: [PHASE_CHARGE_TIME.1=28800 ] line: [PHASE_CHARGE_TIME.1=28800 ; charge time in seconds ] 1:[1] (157) token: [PHASE_CHARGE_TIME.1] value: [28800] 1:[2] (157) token: [PHASE_CHARGE_TIME] array slice: [1] 1:[8] (157): PHASE_CHARGE_TIME=28800 write 28800 @ 7960 1:[8] (157): PHASE_CHARGE_TIME=28800 write 128 @ 7960 1:[8] (157): PHASE_CHARGE_TIME=28800 write 128 @ 7968 1:[1] (158) real: [PHASE_CHARGE_TIME.2=3600 ] line: [PHASE_CHARGE_TIME.2=3600 ; charge time in seconds ] 1:[1] (158) token: [PHASE_CHARGE_TIME.2] value: [3600] 1:[2] (158) token: [PHASE_CHARGE_TIME] array slice: [2] 1:[8] (158): PHASE_CHARGE_TIME=3600 write 3600 @ 7961 1:[8] (158): PHASE_CHARGE_TIME=3600 write 16 @ 7961 1:[8] (158): PHASE_CHARGE_TIME=3600 write 16 @ 7969 1:[1] (159) real: [PHASE_CHARGE_TIME.3=1800 ] line: [PHASE_CHARGE_TIME.3=1800 ; charge time in seconds ] 1:[1] (159) token: [PHASE_CHARGE_TIME.3] value: [1800] 1:[2] (159) token: [PHASE_CHARGE_TIME] array slice: [3] 1:[8] (159): PHASE_CHARGE_TIME=1800 write 1800 @ 7962 1:[8] (159): PHASE_CHARGE_TIME=1800 write 8 @ 7962 1:[8] (159): PHASE_CHARGE_TIME=1800 write 8 @ 7970 1:[1] (160) real: [PHASE_CHARGE_TIME.4=1800 ] line: [PHASE_CHARGE_TIME.4=1800 ; charge time in seconds ] 1:[1] (160) token: [PHASE_CHARGE_TIME.4] value: [1800] 1:[2] (160) token: [PHASE_CHARGE_TIME] array slice: [4] 1:[8] (160): PHASE_CHARGE_TIME=1800 write 1800 @ 7963 1:[8] (160): PHASE_CHARGE_TIME=1800 write 8 @ 7963 1:[8] (160): PHASE_CHARGE_TIME=1800 write 8 @ 7971 1:[1] (161) real: [PHASE_CHARGE_TIME.5=1800 ] line: [PHASE_CHARGE_TIME.5=1800 ; charge time in seconds ] 1:[1] (161) token: [PHASE_CHARGE_TIME.5] value: [1800] 1:[2] (161) token: [PHASE_CHARGE_TIME] array slice: [5] 1:[8] (161): PHASE_CHARGE_TIME=1800 write 1800 @ 7964 1:[8] (161): PHASE_CHARGE_TIME=1800 write 8 @ 7964 1:[8] (161): PHASE_CHARGE_TIME=1800 write 8 @ 7972 1:[1] (162) real: [PHASE_CHARGE_TIME.6=1800 ] line: [PHASE_CHARGE_TIME.6=1800 ; charge time in seconds ] 1:[1] (162) token: [PHASE_CHARGE_TIME.6] value: [1800] 1:[2] (162) token: [PHASE_CHARGE_TIME] array slice: [6] 1:[8] (162): PHASE_CHARGE_TIME=1800 write 1800 @ 7965 1:[8] (162): PHASE_CHARGE_TIME=1800 write 8 @ 7965 1:[8] (162): PHASE_CHARGE_TIME=1800 write 8 @ 7973 1:[1] (163) real: [PHASE_CHARGE_TIME.7=1800 ] line: [PHASE_CHARGE_TIME.7=1800 ; charge time in seconds ] 1:[1] (163) token: [PHASE_CHARGE_TIME.7] value: [1800] 1:[2] (163) token: [PHASE_CHARGE_TIME] array slice: [7] 1:[8] (163): PHASE_CHARGE_TIME=1800 write 1800 @ 7966 1:[8] (163): PHASE_CHARGE_TIME=1800 write 8 @ 7966 1:[8] (163): PHASE_CHARGE_TIME=1800 write 8 @ 7974 1:[1] (164) real: [ ] line: [ ] 1:[1] (165) real: [PHASE_CHARGE_FLAGS.1 = 0 ] line: [PHASE_CHARGE_FLAGS.1 = 0 ] 1:[1] (165) token: [PHASE_CHARGE_FLAGS.1 ] value: [0] 1:[2] (165) token: [PHASE_CHARGE_FLAGS] array slice: [1] 1:[8] (165): PHASE_CHARGE_FLAGS=0 write 0 @ 7952 1:[1] (166) real: [PHASE_CHARGE_FLAGS.2 = 13 ] line: [PHASE_CHARGE_FLAGS.2 = 13 ] 1:[1] (166) token: [PHASE_CHARGE_FLAGS.2 ] value: [13] 1:[2] (166) token: [PHASE_CHARGE_FLAGS] array slice: [2] 1:[8] (166): PHASE_CHARGE_FLAGS=13 write 13 @ 7953 1:[1] (167) real: [PHASE_CHARGE_FLAGS.3 = 13 ] line: [PHASE_CHARGE_FLAGS.3 = 13 ] 1:[1] (167) token: [PHASE_CHARGE_FLAGS.3 ] value: [13] 1:[2] (167) token: [PHASE_CHARGE_FLAGS] array slice: [3] 1:[8] (167): PHASE_CHARGE_FLAGS=13 write 13 @ 7954 1:[1] (168) real: [PHASE_CHARGE_FLAGS.4 = 13 ] line: [PHASE_CHARGE_FLAGS.4 = 13 ] 1:[1] (168) token: [PHASE_CHARGE_FLAGS.4 ] value: [13] 1:[2] (168) token: [PHASE_CHARGE_FLAGS] array slice: [4] 1:[8] (168): PHASE_CHARGE_FLAGS=13 write 13 @ 7955 1:[1] (169) real: [PHASE_CHARGE_FLAGS.5 = 13 ] line: [PHASE_CHARGE_FLAGS.5 = 13 ] 1:[1] (169) token: [PHASE_CHARGE_FLAGS.5 ] value: [13] 1:[2] (169) token: [PHASE_CHARGE_FLAGS] array slice: [5] 1:[8] (169): PHASE_CHARGE_FLAGS=13 write 13 @ 7956 1:[1] (170) real: [PHASE_CHARGE_FLAGS.6 = 13 ] line: [PHASE_CHARGE_FLAGS.6 = 13 ] 1:[1] (170) token: [PHASE_CHARGE_FLAGS.6 ] value: [13] 1:[2] (170) token: [PHASE_CHARGE_FLAGS] array slice: [6] 1:[8] (170): PHASE_CHARGE_FLAGS=13 write 13 @ 7957 1:[1] (171) real: [PHASE_CHARGE_FLAGS.7 = 13 ] line: [PHASE_CHARGE_FLAGS.7 = 13 ] 1:[1] (171) token: [PHASE_CHARGE_FLAGS.7 ] value: [13] 1:[2] (171) token: [PHASE_CHARGE_FLAGS] array slice: [7] 1:[8] (171): PHASE_CHARGE_FLAGS=13 write 13 @ 7958 1:[1] (172) real: [ ] line: [ ] 1:[1] (173) real: [ ] line: [ ; these flags are again a mask (add 'em togeather) ] 1:[1] (174) real: [ ] line: [ ; and they are as follows ] 1:[1] (175) real: [ ] line: [ ; 1 = chg_flag_shutdown, stop charging at the end of this phase ] 1:[1] (176) real: [ ] line: [ ; 2 = chg_flag_temp_comp, use temp compensation ] 1:[1] (177) real: [ ] line: [ ; (see the file temp_comp_explained) ] 1:[1] (178) real: [ ] line: [ ; 4 = chg_flag_didt - if didt starts going up instead of down ] 1:[1] (179) real: [ ] line: [ ; end this phase ] 1:[1] (180) real: [ ] line: [ ; ] 1:[1] (181) real: [ ] line: [ ; 8 = chg_flag_charged - at the end of this phase, set ] 1:[1] (182) real: [ ] line: [ ; the charged system bit ] 1:[1] (183) real: [ ] line: [ ; ] 1:[1] (184) real: [ ] line: [ ; this means the charger will not resume charging until ] 1:[1] (185) real: [ ] line: [ ; the voltage reaches CLEAR_CHARGED_THRESH (going down) ] 1:[1] (186) real: [ ] line: [ ; ] 1:[1] (187) real: [ ] line: [ ] 1:[1] (188) real: [ ] line: [ ; below are the LIMITS ] 1:[1] (189) real: [ ] line: [ ; these are different from the settings in that ] 1:[1] (190) real: [ ] line: [ ; they cause the charger to change phases, ] 1:[1] (191) real: [ ] line: [ ; whereas it will just servo to try and meet the settings ] 1:[1] (192) real: [ ] line: [ ] 1:[1] (193) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.1=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.1=0 ] 1:[1] (193) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.1] value: [0] 1:[2] (193) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [1] 1:[8] (193): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7976 1:[1] (194) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.2=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.2=0 ] 1:[1] (194) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.2] value: [0] 1:[2] (194) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [2] 1:[8] (194): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7977 1:[1] (195) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.3=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.3=0 ] 1:[1] (195) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.3] value: [0] 1:[2] (195) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [3] 1:[8] (195): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7978 1:[1] (196) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.4=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.4=0 ] 1:[1] (196) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.4] value: [0] 1:[2] (196) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [4] 1:[8] (196): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7979 1:[1] (197) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.5=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.5=0 ] 1:[1] (197) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.5] value: [0] 1:[2] (197) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [5] 1:[8] (197): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7980 1:[1] (198) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.6=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.6=0 ] 1:[1] (198) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.6] value: [0] 1:[2] (198) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [6] 1:[8] (198): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7981 1:[1] (199) real: [PHASE_CHARGE_VOLTS_LIMIT_LO.7=0 ] line: [PHASE_CHARGE_VOLTS_LIMIT_LO.7=0 ] 1:[1] (199) token: [PHASE_CHARGE_VOLTS_LIMIT_LO.7] value: [0] 1:[2] (199) token: [PHASE_CHARGE_VOLTS_LIMIT_LO] array slice: [7] 1:[8] (199): PHASE_CHARGE_VOLTS_LIMIT_LO=0 write 0 @ 7982 1:[1] (200) real: [ ] line: [ ] 1:[1] (201) real: [ ] line: [ ; skip to the next phase if voltage falls below the limit ] 1:[1] (202) real: [ ] line: [ ; set here ] 1:[1] (203) real: [ ] line: [ ] 1:[1] (204) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.1=14.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.1=14.5 ] 1:[1] (204) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.1] value: [14.5] 1:[2] (204) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [1] 1:[8] (204): PHASE_CHARGE_VOLTS_LIMIT_HI=14.5 write 187 @ 7984 1:[1] (205) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.2=14.9 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.2=14.9 ] 1:[1] (205) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.2] value: [14.9] 1:[2] (205) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [2] 1:[8] (205): PHASE_CHARGE_VOLTS_LIMIT_HI=14.9 write 195 @ 7985 1:[1] (206) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.3=15.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.3=15.5 ] 1:[1] (206) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.3] value: [15.5] 1:[2] (206) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [3] 1:[8] (206): PHASE_CHARGE_VOLTS_LIMIT_HI=15.5 write 207 @ 7986 1:[1] (207) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.4=15.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.4=15.5 ] 1:[1] (207) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.4] value: [15.5] 1:[2] (207) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [4] 1:[8] (207): PHASE_CHARGE_VOLTS_LIMIT_HI=15.5 write 207 @ 7987 1:[1] (208) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.5=15.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.5=15.5 ] 1:[1] (208) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.5] value: [15.5] 1:[2] (208) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [5] 1:[8] (208): PHASE_CHARGE_VOLTS_LIMIT_HI=15.5 write 207 @ 7988 1:[1] (209) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.6=15.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.6=15.5 ] 1:[1] (209) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.6] value: [15.5] 1:[2] (209) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [6] 1:[8] (209): PHASE_CHARGE_VOLTS_LIMIT_HI=15.5 write 207 @ 7989 1:[1] (210) real: [PHASE_CHARGE_VOLTS_LIMIT_HI.7=15.5 ] line: [PHASE_CHARGE_VOLTS_LIMIT_HI.7=15.5 ] 1:[1] (210) token: [PHASE_CHARGE_VOLTS_LIMIT_HI.7] value: [15.5] 1:[2] (210) token: [PHASE_CHARGE_VOLTS_LIMIT_HI] array slice: [7] 1:[8] (210): PHASE_CHARGE_VOLTS_LIMIT_HI=15.5 write 207 @ 7990 1:[1] (211) real: [ ] line: [ ] 1:[1] (212) real: [ ] line: [ ; skip to the next phase if voltage falls below the limit ] 1:[1] (213) real: [ ] line: [ ; set here ] 1:[1] (214) real: [ ] line: [ ] 1:[1] (215) real: [PHASE_CHARGE_AMPS_LIMIT_LO.1=1.0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.1=1.0 ] 1:[1] (215) token: [PHASE_CHARGE_AMPS_LIMIT_LO.1] value: [1.0] 1:[2] (215) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [1] 1:[8] (215): PHASE_CHARGE_AMPS_LIMIT_LO=1.0 write 10 @ 7992 1:[1] (216) real: [PHASE_CHARGE_AMPS_LIMIT_LO.2=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.2=0 ] 1:[1] (216) token: [PHASE_CHARGE_AMPS_LIMIT_LO.2] value: [0] 1:[2] (216) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [2] 1:[8] (216): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7993 1:[1] (217) real: [PHASE_CHARGE_AMPS_LIMIT_LO.3=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.3=0 ] 1:[1] (217) token: [PHASE_CHARGE_AMPS_LIMIT_LO.3] value: [0] 1:[2] (217) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [3] 1:[8] (217): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7994 1:[1] (218) real: [PHASE_CHARGE_AMPS_LIMIT_LO.4=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.4=0 ] 1:[1] (218) token: [PHASE_CHARGE_AMPS_LIMIT_LO.4] value: [0] 1:[2] (218) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [4] 1:[8] (218): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7995 1:[1] (219) real: [PHASE_CHARGE_AMPS_LIMIT_LO.5=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.5=0 ] 1:[1] (219) token: [PHASE_CHARGE_AMPS_LIMIT_LO.5] value: [0] 1:[2] (219) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [5] 1:[8] (219): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7996 1:[1] (220) real: [PHASE_CHARGE_AMPS_LIMIT_LO.6=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.6=0 ] 1:[1] (220) token: [PHASE_CHARGE_AMPS_LIMIT_LO.6] value: [0] 1:[2] (220) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [6] 1:[8] (220): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7997 1:[1] (221) real: [PHASE_CHARGE_AMPS_LIMIT_LO.7=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_LO.7=0 ] 1:[1] (221) token: [PHASE_CHARGE_AMPS_LIMIT_LO.7] value: [0] 1:[2] (221) token: [PHASE_CHARGE_AMPS_LIMIT_LO] array slice: [7] 1:[8] (221): PHASE_CHARGE_AMPS_LIMIT_LO=0 write 0 @ 7998 1:[1] (222) real: [ ] line: [ ] 1:[1] (223) real: [ ] line: [ ; skip to the next phase if amperage falls below the limit ] 1:[1] (224) real: [ ] line: [ ; set here ] 1:[1] (225) real: [ ] line: [ ] 1:[1] (226) real: [PHASE_CHARGE_AMPS_LIMIT_HI.1=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.1=0 ] 1:[1] (226) token: [PHASE_CHARGE_AMPS_LIMIT_HI.1] value: [0] 1:[2] (226) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [1] 1:[8] (226): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8000 1:[1] (227) real: [PHASE_CHARGE_AMPS_LIMIT_HI.2=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.2=0 ] 1:[1] (227) token: [PHASE_CHARGE_AMPS_LIMIT_HI.2] value: [0] 1:[2] (227) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [2] 1:[8] (227): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8001 1:[1] (228) real: [PHASE_CHARGE_AMPS_LIMIT_HI.3=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.3=0 ] 1:[1] (228) token: [PHASE_CHARGE_AMPS_LIMIT_HI.3] value: [0] 1:[2] (228) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [3] 1:[8] (228): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8002 1:[1] (229) real: [PHASE_CHARGE_AMPS_LIMIT_HI.4=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.4=0 ] 1:[1] (229) token: [PHASE_CHARGE_AMPS_LIMIT_HI.4] value: [0] 1:[2] (229) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [4] 1:[8] (229): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8003 1:[1] (230) real: [PHASE_CHARGE_AMPS_LIMIT_HI.5=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.5=0 ] 1:[1] (230) token: [PHASE_CHARGE_AMPS_LIMIT_HI.5] value: [0] 1:[2] (230) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [5] 1:[8] (230): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8004 1:[1] (231) real: [PHASE_CHARGE_AMPS_LIMIT_HI.6=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.6=0 ] 1:[1] (231) token: [PHASE_CHARGE_AMPS_LIMIT_HI.6] value: [0] 1:[2] (231) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [6] 1:[8] (231): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8005 1:[1] (232) real: [PHASE_CHARGE_AMPS_LIMIT_HI.7=0 ] line: [PHASE_CHARGE_AMPS_LIMIT_HI.7=0 ] 1:[1] (232) token: [PHASE_CHARGE_AMPS_LIMIT_HI.7] value: [0] 1:[2] (232) token: [PHASE_CHARGE_AMPS_LIMIT_HI] array slice: [7] 1:[8] (232): PHASE_CHARGE_AMPS_LIMIT_HI=0 write 0 @ 8006 1:[1] (233) real: [ ] line: [ ] 1:[1] (234) real: [ ] line: [ ; skip to the next phase if amperage goes above the limit ] 1:[1] (235) real: [ ] line: [ ; set here ] 1:[1] (236) real: [ ] line: [ ] 1:[1] (237) real: [PHASE_CHARGE_TEMP_LIMIT_LO.1=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.1=0 ] 1:[1] (237) token: [PHASE_CHARGE_TEMP_LIMIT_LO.1] value: [0] 1:[2] (237) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [1] 1:[8] (237): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8008 1:[1] (238) real: [PHASE_CHARGE_TEMP_LIMIT_LO.2=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.2=0 ] 1:[1] (238) token: [PHASE_CHARGE_TEMP_LIMIT_LO.2] value: [0] 1:[2] (238) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [2] 1:[8] (238): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8009 1:[1] (239) real: [PHASE_CHARGE_TEMP_LIMIT_LO.3=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.3=0 ] 1:[1] (239) token: [PHASE_CHARGE_TEMP_LIMIT_LO.3] value: [0] 1:[2] (239) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [3] 1:[8] (239): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8010 1:[1] (240) real: [PHASE_CHARGE_TEMP_LIMIT_LO.4=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.4=0 ] 1:[1] (240) token: [PHASE_CHARGE_TEMP_LIMIT_LO.4] value: [0] 1:[2] (240) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [4] 1:[8] (240): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8011 1:[1] (241) real: [PHASE_CHARGE_TEMP_LIMIT_LO.5=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.5=0 ] 1:[1] (241) token: [PHASE_CHARGE_TEMP_LIMIT_LO.5] value: [0] 1:[2] (241) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [5] 1:[8] (241): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8012 1:[1] (242) real: [PHASE_CHARGE_TEMP_LIMIT_LO.6=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.6=0 ] 1:[1] (242) token: [PHASE_CHARGE_TEMP_LIMIT_LO.6] value: [0] 1:[2] (242) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [6] 1:[8] (242): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8013 1:[1] (243) real: [PHASE_CHARGE_TEMP_LIMIT_LO.7=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_LO.7=0 ] 1:[1] (243) token: [PHASE_CHARGE_TEMP_LIMIT_LO.7] value: [0] 1:[2] (243) token: [PHASE_CHARGE_TEMP_LIMIT_LO] array slice: [7] 1:[8] (243): PHASE_CHARGE_TEMP_LIMIT_LO=0 write 0 @ 8014 1:[1] (244) real: [ ] line: [ ] 1:[1] (245) real: [ ] line: [ ; skip to the next phase if temp goes below the limit set here ] 1:[1] (246) real: [ ] line: [ ; note that '0' is reserved to mean 'no limit' ] 1:[1] (247) real: [ ] line: [ ; try setting it to 1 if you want to stop ] 1:[1] (248) real: [ ] line: [ ; 31 degrees below where water freezes ] 1:[1] (249) real: [ ] line: [ ] 1:[1] (250) real: [ ] line: [ ; (et cetera) ] 1:[1] (251) real: [ ] line: [ ] 1:[1] (252) real: [PHASE_CHARGE_TEMP_LIMIT_HI.1=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.1=0 ] 1:[1] (252) token: [PHASE_CHARGE_TEMP_LIMIT_HI.1] value: [0] 1:[2] (252) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [1] 1:[8] (252): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8016 1:[1] (253) real: [PHASE_CHARGE_TEMP_LIMIT_HI.2=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.2=0 ] 1:[1] (253) token: [PHASE_CHARGE_TEMP_LIMIT_HI.2] value: [0] 1:[2] (253) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [2] 1:[8] (253): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8017 1:[1] (254) real: [PHASE_CHARGE_TEMP_LIMIT_HI.3=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.3=0 ] 1:[1] (254) token: [PHASE_CHARGE_TEMP_LIMIT_HI.3] value: [0] 1:[2] (254) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [3] 1:[8] (254): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8018 1:[1] (255) real: [PHASE_CHARGE_TEMP_LIMIT_HI.4=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.4=0 ] 1:[1] (255) token: [PHASE_CHARGE_TEMP_LIMIT_HI.4] value: [0] 1:[2] (255) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [4] 1:[8] (255): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8019 1:[1] (256) real: [PHASE_CHARGE_TEMP_LIMIT_HI.5=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.5=0 ] 1:[1] (256) token: [PHASE_CHARGE_TEMP_LIMIT_HI.5] value: [0] 1:[2] (256) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [5] 1:[8] (256): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8020 1:[1] (257) real: [PHASE_CHARGE_TEMP_LIMIT_HI.6=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.6=0 ] 1:[1] (257) token: [PHASE_CHARGE_TEMP_LIMIT_HI.6] value: [0] 1:[2] (257) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [6] 1:[8] (257): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8021 1:[1] (258) real: [PHASE_CHARGE_TEMP_LIMIT_HI.7=0 ] line: [PHASE_CHARGE_TEMP_LIMIT_HI.7=0 ] 1:[1] (258) token: [PHASE_CHARGE_TEMP_LIMIT_HI.7] value: [0] 1:[2] (258) token: [PHASE_CHARGE_TEMP_LIMIT_HI] array slice: [7] 1:[8] (258): PHASE_CHARGE_TEMP_LIMIT_HI=0 write 0 @ 8022 1:[1] (259) real: [ ] line: [ ] 1:[1] (260) real: [ ] line: [ ; skip to the next phase if temp goes above te limit set here ] 1:[1] (261) real: [ ] line: [ ; see notes on LIMIT_LO ] 1:[1] (262) real: [ ] line: [ ] 1:[1] (263) real: [] line: [;VOLTS_M=0 ] 1:[1] (264) real: [] line: [;VOLTS_C=0 ] 1:[1] (265) real: [] line: [;VOLTS_B=0 ] 1:[1] (266) real: [] line: [;AMPS_M=0 ] 1:[1] (267) real: [] line: [;AMPS_C=0 ] 1:[1] (268) real: [] line: [;AMPS_B=0 ] 1:[1] (269) real: [] line: [;VOLTS_HV_M=0 ] 1:[1] (270) real: [] line: [;VOLTS_HV_C=0 ] 1:[1] (271) real: [] line: [;VOLTS_HV_B=0 ] 1:[1] (272) real: [] line: [; these are all special calibration values ] 1:[1] (273) real: [] line: [; noramlly you will set them with the calibration routines ] 1:[1] (274) real: [] line: [; calibrate_volts ] 1:[1] (275) real: [] line: [; calibrate_amps ] 1:[1] (276) real: [] line: [; calibrate_hv ] 1:[1] (277) real: [] line: [; ] 1:[1] (278) real: [] line: [; this is just included in case you need a fast way to rough cal a board ] 1:[1] (279) real: [] line: [; the function read_calibration will print out these values ] 1:[1] (280) real: [] line: [; if you want them ] 1:[1] (281) real: [ ] line: [ ] 1:[1] (282) real: [] line: [; here's a example of loading the temp compensation table ] 1:[1] (283) real: [] line: [; through the config file - lee, take note! I may not have time to write ] 1:[1] (284) real: [] line: [; a parser for your file format! ] 1:[1] (285) real: [] line: [; ] 1:[1] (286) real: [ ] line: [ ] 1:[1] (287) real: [TEMP_LOOKUP.119 = 80 ] line: [TEMP_LOOKUP.119 = 80 ] 1:[1] (287) token: [TEMP_LOOKUP.119 ] value: [80] 1:[2] (287) token: [TEMP_LOOKUP] array slice: [119] 1:[8] (287): TEMP_LOOKUP=80 write 80 @ 7798 1:[1] (288) real: [TEMP_LOOKUP.120 = 80 ] line: [TEMP_LOOKUP.120 = 80 ] 1:[1] (288) token: [TEMP_LOOKUP.120 ] value: [80] 1:[2] (288) token: [TEMP_LOOKUP] array slice: [120] 1:[8] (288): TEMP_LOOKUP=80 write 80 @ 7799 1:[1] (289) real: [TEMP_LOOKUP.121 = 80 ] line: [TEMP_LOOKUP.121 = 80 ] 1:[1] (289) token: [TEMP_LOOKUP.121 ] value: [80] 1:[2] (289) token: [TEMP_LOOKUP] array slice: [121] 1:[8] (289): TEMP_LOOKUP=80 write 80 @ 7800 1:[1] (290) real: [TEMP_LOOKUP.122 = 80 ] line: [TEMP_LOOKUP.122 = 80 ] 1:[1] (290) token: [TEMP_LOOKUP.122 ] value: [80] 1:[2] (290) token: [TEMP_LOOKUP] array slice: [122] 1:[8] (290): TEMP_LOOKUP=80 write 80 @ 7801 1:[1] (291) real: [TEMP_LOOKUP.123 = 80 ] line: [TEMP_LOOKUP.123 = 80 ] 1:[1] (291) token: [TEMP_LOOKUP.123 ] value: [80] 1:[2] (291) token: [TEMP_LOOKUP] array slice: [123] 1:[8] (291): TEMP_LOOKUP=80 write 80 @ 7802 1:[1] (292) real: [TEMP_LOOKUP.124 = 80 ] line: [TEMP_LOOKUP.124 = 80 ] 1:[1] (292) token: [TEMP_LOOKUP.124 ] value: [80] 1:[2] (292) token: [TEMP_LOOKUP] array slice: [124] 1:[8] (292): TEMP_LOOKUP=80 write 80 @ 7803 1:[1] (293) real: [TEMP_LOOKUP.125 = 81 ] line: [TEMP_LOOKUP.125 = 81 ] 1:[1] (293) token: [TEMP_LOOKUP.125 ] value: [81] 1:[2] (293) token: [TEMP_LOOKUP] array slice: [125] 1:[8] (293): TEMP_LOOKUP=81 write 81 @ 7804 1:[1] (294) real: [TEMP_LOOKUP.126 = 82 ] line: [TEMP_LOOKUP.126 = 82 ] 1:[1] (294) token: [TEMP_LOOKUP.126 ] value: [82] 1:[2] (294) token: [TEMP_LOOKUP] array slice: [126] 1:[8] (294): TEMP_LOOKUP=82 write 82 @ 7805 1:[1] (295) real: [TEMP_LOOKUP.127 = 83 ] line: [TEMP_LOOKUP.127 = 83 ] 1:[1] (295) token: [TEMP_LOOKUP.127 ] value: [83] 1:[2] (295) token: [TEMP_LOOKUP] array slice: [127] 1:[8] (295): TEMP_LOOKUP=83 write 83 @ 7806 1:[1] (296) real: [TEMP_LOOKUP.128 = 84 ] line: [TEMP_LOOKUP.128 = 84 ] 1:[1] (296) token: [TEMP_LOOKUP.128 ] value: [84] 1:[2] (296) token: [TEMP_LOOKUP] array slice: [128] 1:[8] (296): TEMP_LOOKUP=84 write 84 @ 7807 1:[1] (297) real: [TEMP_LOOKUP.129 = 85 ] line: [TEMP_LOOKUP.129 = 85 ] 1:[1] (297) token: [TEMP_LOOKUP.129 ] value: [85] 1:[2] (297) token: [TEMP_LOOKUP] array slice: [129] 1:[8] (297): TEMP_LOOKUP=85 write 85 @ 7808 1:[1] (298) real: [TEMP_LOOKUP.130 = 86 ] line: [TEMP_LOOKUP.130 = 86 ] 1:[1] (298) token: [TEMP_LOOKUP.130 ] value: [86] 1:[2] (298) token: [TEMP_LOOKUP] array slice: [130] 1:[8] (298): TEMP_LOOKUP=86 write 86 @ 7809 1:[1] (299) real: [ ] line: [ ] 1:[1] (300) real: [] line: [;TEMP_LOOKUP.(0-255)=(temp) - this is how you map ] 1:[1] (301) real: [] line: [; temp sensor A/D values into real world temps ] 1:[1] (302) real: [] line: [; ] 1:[1] (303) real: [] line: [;TEMP_COMP.(0-255)=(volts) ] 1:[1] (304) real: [] line: [; this is how you apply corrections for voltage ] 1:[1] (305) real: [] line: [; based on temp comp (if the right CHARGE_PHASE_FLAG is set) ] 1:[1] (306) real: [] line: [; ] 1:[1] (307) real: [] line: [; note that the value here is thousandths of a volt ] 1:[1] (308) real: [] line: [; and that it is ADDED to the REPORTED VOLTAGE OF THE OPTIMA ] 1:[1] (309) real: [] line: [; ] 1:[1] (310) real: [] line: [; this means to make it so at ten degrees F, the charger would switch ] 1:[1] (311) real: [] line: [; off a tenth of a volt later, you would use a NEGATIVE number ] 1:[1] (312) real: [] line: [; ] 1:[1] (313) real: [] line: [; i.e. ] 1:[1] (314) real: [] line: [; TEMP_COMP.10=-100 ] 1:[1] (315) real: [] line: [; note also that the subscript is binary ] 1:[1] (316) real: [] line: [; so -40 degrees = 0, 0 degrees = 40, 40 degrees = 80, etc ] 1:[1] (317) real: [ ] line: [ ] 1:[1] (318) real: [TURN_ON_BALANCE_HV=0 ] line: [TURN_ON_BALANCE_HV=0 ; this is the HV voltage at which we go to the phase below ] 1:[1] (318) token: [TURN_ON_BALANCE_HV] value: [0] 1:[8] (318): TURN_ON_BALANCE_HV=0 write 0 @ 8118 1:[1] (319) real: [TURN_ON_BALANCE_PHASE=0 ] line: [TURN_ON_BALANCE_PHASE=0 ] 1:[1] (319) token: [TURN_ON_BALANCE_PHASE] value: [0] 1:[8] (319): TURN_ON_BALANCE_PHASE=0 write 0 @ 8120 1:[1] (320) real: [ ] line: [ ] 1:[1] (321) real: [TURN_ON_CHARGE_HV=310 ] line: [TURN_ON_CHARGE_HV=310 ; this is the HV voltage at which we go to the phase below ] 1:[1] (321) token: [TURN_ON_CHARGE_HV] value: [310] 1:[8] (321): TURN_ON_CHARGE_HV=310 write 155 @ 8119 1:[1] (322) real: [TURN_ON_CHARGE_PHASE=1 ] line: [TURN_ON_CHARGE_PHASE=1 ] 1:[1] (322) token: [TURN_ON_CHARGE_PHASE] value: [1] 1:[8] (322): TURN_ON_CHARGE_PHASE=1 write 1 @ 8121 1:[1] (323) real: [ ] line: [ ] 1:[1] (324) real: [TURN_OFF_CHARGE_HV=240 ] line: [TURN_OFF_CHARGE_HV=240 ; this is the voltage at which we will turn off the charger ] 1:[1] (324) token: [TURN_OFF_CHARGE_HV] value: [240] 1:[8] (324): TURN_OFF_CHARGE_HV=240 write 120 @ 8122 1:[1] (325) real: [ ] line: [ ; if it is set ] 1:[1] (326) real: [ ] line: [ ] 1:[1] (327) real: [ ] line: [ ; note that if this is below the balance voltage ] 1:[1] (328) real: [ ] line: [ ; the charger will immediately hop to balance mode ] 1:[1] (329) real: [ ] line: [ ] 1:[1] (330) real: [TURN_OFF_BALANCE_HV=0 ] line: [TURN_OFF_BALANCE_HV=0 ; this is the voltage at which we will turn off auto ] 1:[1] (330) token: [TURN_OFF_BALANCE_HV] value: [0] 1:[8] (330): TURN_OFF_BALANCE_HV=0 write 0 @ 8032 1:[1] (331) real: [ ] line: [ ; balance if it is engaged ] 1:[1] (332) real: [ ] line: [ ; note that this and charge can ] 1:[1] (333) real: [ ] line: [ ; interact in strange ways ] 1:[1] (334) real: [ ] line: [ ] 1:[1] (335) real: [BALANCE_NUM_BATTERIES_PHASE=0 ] line: [BALANCE_NUM_BATTERIES_PHASE=0 ; ask lee. it was his idea ] 1:[1] (335) token: [BALANCE_NUM_BATTERIES_PHASE] value: [0] 1:[8] (335): BALANCE_NUM_BATTERIES_PHASE=0 write 0 @ 8105 1:[1] (336) real: [BALANCE_NUM_BATTERIES=25 ] line: [BALANCE_NUM_BATTERIES=25 ; ask lee. it was his idea ] 1:[1] (336) token: [BALANCE_NUM_BATTERIES] value: [25] 1:[8] (336): BALANCE_NUM_BATTERIES=25 write 25 @ 8104 1:[1] (337) real: [ ] line: [ ] 1:[1] (338) real: [CLEAR_CHARGED_THRESH=12.8 ] line: [CLEAR_CHARGED_THRESH=12.8 ; at this voltage, we will clear ] 1:[1] (338) token: [CLEAR_CHARGED_THRESH] value: [12.8] 1:[8] (338): CLEAR_CHARGED_THRESH=12.8 write 153 @ 8123 1:[1] (339) real: [ ] line: [ ; the charged bit, causing the charger ] 1:[1] (340) real: [ ] line: [ ; to resume automatic charging ] 1:[1] (341) real: [ ] line: [ ] 1:[1] (342) real: [ ] line: [ ; please note that the DIDT routines ] 1:[1] (343) real: [ ] line: [ ; are only suitable for charge phases ] 1:[1] (344) real: [ ] line: [ ; that should start out at their ] 1:[1] (345) real: [ ] line: [ ; maximum amps, and slowly scale down ] 1:[1] (346) real: [ ] line: [ ] 1:[1] (347) real: [DIDT_WINDOW=100 ] line: [DIDT_WINDOW=100 ; ignore didt for this many seconds ] 1:[1] (347) token: [DIDT_WINDOW] value: [100] 1:[8] (347): DIDT_WINDOW=100 write 100 @ 8124 1:[1] (348) real: [ ] line: [ ; (gives the charger a chance to stablize) ] 1:[1] (349) real: [ ] line: [ ] 1:[1] (350) real: [DIDT_UP_LIMIT=5 ] line: [DIDT_UP_LIMIT=5 ; allow the DIDT to raise this many times ] 1:[1] (350) token: [DIDT_UP_LIMIT] value: [5] 1:[8] (350): DIDT_UP_LIMIT=5 write 5 @ 8125 1:[1] (351) real: [ ] line: [ ; (or stay raised for this many minutes) ] 1:[1] (352) real: [DIDT_CLIMB=1 ] line: [DIDT_CLIMB=1 ] 1:[1] (352) token: [DIDT_CLIMB] value: [1] 1:[8] (352): DIDT_CLIMB=1 write 1 @ 8126 1:[1] (353) real: [ ] line: [ ] 1:[1] (354) real: [BEEP_ON_NET_TIMEOUT=1 ] line: [BEEP_ON_NET_TIMEOUT=1 ; debugging feature ] 1:[1] (354) token: [BEEP_ON_NET_TIMEOUT] value: [1] 1:[8] (354): BEEP_ON_NET_TIMEOUT=1 write 1 @ 8127 1:[1] (355) real: [ ] line: [ ] 1:[1] (356) real: [BAUD_LOCKED=69 ] line: [BAUD_LOCKED=69 ; if this is not 69 ] 1:[1] (356) token: [BAUD_LOCKED] value: [69] 1:[8] (356): BAUD_LOCKED=69 write 69 @ 8106 1:[1] (357) real: [ ] line: [ ; all reboots will return BAUD to 9600 ] 1:[1] (358) real: [ ] line: [ ] 1:[1] (359) real: [BAUD=9600 ] line: [BAUD=9600 ; set the baud rate the charger will respond to ] 1:[1] (359) token: [BAUD] value: [9600] 1:[8] (359): BAUD=9600 write 8 @ 8107 1:[1] (360) real: [ ] line: [ ; requires a reboot to take effect ] 1:[1] (361) real: [ ] line: [ ; ] 1:[1] (362) real: [ ] line: [ ; note that if this is not 9600, reloading ] 1:[1] (363) real: [ ] line: [ ; the software on the VESTA with the IDE ] 1:[1] (364) real: [ ] line: [ ; may prove challenging ] 1:[1] (365) real: [ ] line: [ ] 1:[1] (366) real: [MIN_VOLTS=6.0 ] line: [MIN_VOLTS=6.0 ; voltage below which a undervolt ] 1:[1] (366) token: [MIN_VOLTS] value: [6.0] 1:[8] (366): MIN_VOLTS=6.0 write 17 @ 8111 1:[1] (367) real: [ ] line: [ ; error will be recorded ] 1:[1] (368) real: [ ] line: [ ] 1:[1] (369) real: [MIN_BATT_TEMP=0 ] line: [MIN_BATT_TEMP=0 ; batt temp below hwich ] 1:[1] (369) token: [MIN_BATT_TEMP] value: [0] 1:[8] (369): MIN_BATT_TEMP=0 write 0 @ 8110 1:[1] (370) real: [ ] line: [ ; a error will be recorded ] 1:[1] (371) real: [ ] line: [ ; (see the notes about batt temps elsewhere) ] 1:[1] (372) real: [ ] line: [ ] 1:[1] (373) real: [MIN_CHG_TEMP=100 ] line: [MIN_CHG_TEMP=100 ; sensor value above which a ] 1:[1] (373) token: [MIN_CHG_TEMP] value: [100] 1:[8] (373): MIN_CHG_TEMP=100 write 100 @ 8109 1:[1] (374) real: [ ] line: [ ; fault will be recorded ] 4:[4] write_ram(40947,55) [243/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f3 (243) [d1 ] Write lo addr 4:[1] WRTE:4: 37 (55) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2a (42) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f3 (243) [d2 ] 4:[1] read<5: 37 (55) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2a (42) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f3 (243) [d2 ] 4:[2] write_ram:5: 37 (55) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f3 (243) [d1 ] Write lo addr 4:[1] WRTE:4: 37 (55) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f3 (243) [d1 ] Write lo addr 4:[2] write_ram_return:4: 37 (55) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f3 (243) [d1 ] Write lo addr 4:[1] read<4: 37 (55) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7798: -> 80 2:[2] 7799: -> 80 2:[2] 7800: -> 80 2:[2] 7801: -> 80 2:[8] 7798: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1e (30) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 76 (118) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 76 (118) [d0 ] 4:[1] read<3: 1e (30) [d1 ] 4:[1] read<4: 76 (118) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1e (30) [d0 ] address 0xFF00 4:[1] WRTE:3: 76 (118) [d1 ] address 0x00FF 4:[1] WRTE:4: 50 (80) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 50 (80) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 50 (80) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 50 (80) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7802: -> 80 2:[2] 7803: -> 80 2:[2] 7804: -> 81 2:[2] 7805: -> 82 2:[8] 7802: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1e (30) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 7a (122) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 7a (122) [d0 ] 4:[1] read<3: 1e (30) [d1 ] 4:[1] read<4: 7a (122) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1e (30) [d0 ] address 0xFF00 4:[1] WRTE:3: 7a (122) [d1 ] address 0x00FF 4:[1] WRTE:4: 50 (80) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 50 (80) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 51 (81) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 52 (82) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7806: -> 83 2:[2] 7807: -> 84 2:[2] 7808: -> 85 2:[2] 7809: -> 86 2:[8] 7806: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1e (30) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 7e (126) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 7e (126) [d0 ] 4:[1] read<3: 1e (30) [d1 ] 4:[1] read<4: 7e (126) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1e (30) [d0 ] address 0xFF00 4:[1] WRTE:3: 7e (126) [d1 ] address 0x00FF 4:[1] WRTE:4: 53 (83) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 54 (84) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 55 (85) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 56 (86) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7936: PHASE_CHARGE_VOLTS -> 191 2:[2] 7937: -> 233 2:[2] 7938: -> 177 2:[2] 7939: -> 177 2:[8] 7936: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 0 (0) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 0 (0) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 0 (0) [d1 ] address 0x00FF 4:[1] WRTE:4: bf (191) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: e9 (233) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: b1 (177) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: b1 (177) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7940: not big enough for chunk (3) 2:[2] 7940: -> 177 4:[4] write_ram(40708,177) [4/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4 (4) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: b5 (181) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 4 (4) [d2 ] 4:[1] read<5: b1 (177) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: b5 (181) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 4 (4) [d2 ] 4:[2] write_ram:5: b1 (177) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4 (4) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 4 (4) [d1 ] Write lo addr 4:[2] write_ram_return:4: b1 (177) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 4 (4) [d1 ] Write lo addr 4:[1] read<4: b1 (177) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7941: not big enough for chunk (3) 2:[2] 7941: -> 177 4:[4] write_ram(40709,177) [5/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 5 (5) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: b6 (182) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 5 (5) [d2 ] 4:[1] read<5: b1 (177) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: b6 (182) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 5 (5) [d2 ] 4:[2] write_ram:5: b1 (177) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 5 (5) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 5 (5) [d1 ] Write lo addr 4:[2] write_ram_return:4: b1 (177) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 5 (5) [d1 ] Write lo addr 4:[1] read<4: b1 (177) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7942: not big enough for chunk (3) 2:[2] 7942: -> 177 4:[4] write_ram(40710,177) [6/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 6 (6) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: b7 (183) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 6 (6) [d2 ] 4:[1] read<5: b1 (177) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: b7 (183) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 6 (6) [d2 ] 4:[2] write_ram:5: b1 (177) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 6 (6) [d1 ] Write lo addr 4:[1] WRTE:4: b1 (177) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 6 (6) [d1 ] Write lo addr 4:[2] write_ram_return:4: b1 (177) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 6 (6) [d1 ] Write lo addr 4:[1] read<4: b1 (177) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7944: PHASE_CHARGE_AMPS -> 100 2:[2] 7945: -> 20 2:[2] 7946: -> 25 2:[2] 7947: -> 0 2:[8] 7944: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 8 (8) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 8 (8) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 8 (8) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 8 (8) [d1 ] address 0x00FF 4:[1] WRTE:4: 64 (100) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 14 (20) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 19 (25) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7948: not big enough for chunk (3) 2:[2] 7948: -> 0 4:[4] write_ram(40716,0) [12/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: c (12) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: c (12) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: c (12) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: c (12) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: c (12) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: c (12) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: c (12) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: c (12) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7949: not big enough for chunk (3) 2:[2] 7949: -> 0 4:[4] write_ram(40717,0) [13/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: d (13) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: d (13) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: d (13) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: d (13) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: d (13) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: d (13) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: d (13) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: d (13) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7950: not big enough for chunk (3) 2:[2] 7950: -> 0 4:[4] write_ram(40718,0) [14/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: e (14) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: e (14) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: e (14) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: e (14) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: e (14) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: e (14) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: e (14) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: e (14) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7952: PHASE_CHARGE_FLAGS -> 0 2:[2] 7953: -> 13 2:[2] 7954: -> 13 2:[2] 7955: -> 13 2:[8] 7952: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 10 (16) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 10 (16) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 10 (16) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 10 (16) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: d (13) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: d (13) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: d (13) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7956: not big enough for chunk (3) 2:[2] 7956: -> 13 4:[4] write_ram(40724,13) [20/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 14 (20) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 21 (33) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 14 (20) [d2 ] 4:[1] read<5: d (13) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 21 (33) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 14 (20) [d2 ] 4:[2] write_ram:5: d (13) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 14 (20) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 14 (20) [d1 ] Write lo addr 4:[2] write_ram_return:4: d (13) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 14 (20) [d1 ] Write lo addr 4:[1] read<4: d (13) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7957: not big enough for chunk (3) 2:[2] 7957: -> 13 4:[4] write_ram(40725,13) [21/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 15 (21) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 22 (34) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 15 (21) [d2 ] 4:[1] read<5: d (13) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 22 (34) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 15 (21) [d2 ] 4:[2] write_ram:5: d (13) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 15 (21) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 15 (21) [d1 ] Write lo addr 4:[2] write_ram_return:4: d (13) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 15 (21) [d1 ] Write lo addr 4:[1] read<4: d (13) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7958: not big enough for chunk (3) 2:[2] 7958: -> 13 4:[4] write_ram(40726,13) [22/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 16 (22) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 23 (35) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 16 (22) [d2 ] 4:[1] read<5: d (13) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 23 (35) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 16 (22) [d2 ] 4:[2] write_ram:5: d (13) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 16 (22) [d1 ] Write lo addr 4:[1] WRTE:4: d (13) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 16 (22) [d1 ] Write lo addr 4:[2] write_ram_return:4: d (13) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 16 (22) [d1 ] Write lo addr 4:[1] read<4: d (13) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7960: PHASE_CHARGE_TIME -> 128 2:[2] 7961: -> 16 2:[2] 7962: -> 8 2:[2] 7963: -> 8 2:[8] 7960: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 18 (24) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 18 (24) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 18 (24) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 18 (24) [d1 ] address 0x00FF 4:[1] WRTE:4: 80 (128) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 10 (16) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 8 (8) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 8 (8) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7964: not big enough for chunk (3) 2:[2] 7964: -> 8 4:[4] write_ram(40732,8) [28/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1c (28) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 24 (36) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 1c (28) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 24 (36) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 1c (28) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1c (28) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 1c (28) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 1c (28) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7965: not big enough for chunk (3) 2:[2] 7965: -> 8 4:[4] write_ram(40733,8) [29/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1d (29) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 25 (37) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 1d (29) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 25 (37) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 1d (29) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1d (29) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 1d (29) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 1d (29) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7966: not big enough for chunk (3) 2:[2] 7966: -> 8 4:[4] write_ram(40734,8) [30/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1e (30) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 26 (38) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 1e (30) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 26 (38) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 1e (30) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 1e (30) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 1e (30) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 1e (30) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7968: PHASE_CHARGE_TIME_HI -> 128 2:[2] 7969: -> 16 2:[2] 7970: -> 8 2:[2] 7971: -> 8 2:[8] 7968: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 20 (32) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 20 (32) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 20 (32) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 20 (32) [d1 ] address 0x00FF 4:[1] WRTE:4: 80 (128) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 10 (16) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 8 (8) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 8 (8) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7972: not big enough for chunk (3) 2:[2] 7972: -> 8 4:[4] write_ram(40740,8) [36/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 24 (36) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2c (44) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 24 (36) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2c (44) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 24 (36) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 24 (36) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 24 (36) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 24 (36) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7973: not big enough for chunk (3) 2:[2] 7973: -> 8 4:[4] write_ram(40741,8) [37/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 25 (37) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2d (45) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 25 (37) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2d (45) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 25 (37) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 25 (37) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 25 (37) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 25 (37) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7974: not big enough for chunk (3) 2:[2] 7974: -> 8 4:[4] write_ram(40742,8) [38/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 26 (38) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2e (46) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 26 (38) [d2 ] 4:[1] read<5: 8 (8) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2e (46) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 26 (38) [d2 ] 4:[2] write_ram:5: 8 (8) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 26 (38) [d1 ] Write lo addr 4:[1] WRTE:4: 8 (8) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 26 (38) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8 (8) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 26 (38) [d1 ] Write lo addr 4:[1] read<4: 8 (8) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7976: PHASE_CHARGE_VOLTS_LIMIT_LO -> 0 2:[2] 7977: -> 0 2:[2] 7978: -> 0 2:[2] 7979: -> 0 2:[8] 7976: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 28 (40) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 28 (40) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 28 (40) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 28 (40) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7980: not big enough for chunk (3) 2:[2] 7980: -> 0 4:[4] write_ram(40748,0) [44/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2c (44) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2c (44) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 2c (44) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2c (44) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 2c (44) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2c (44) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 2c (44) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 2c (44) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7981: not big enough for chunk (3) 2:[2] 7981: -> 0 4:[4] write_ram(40749,0) [45/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2d (45) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2d (45) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 2d (45) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2d (45) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 2d (45) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2d (45) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 2d (45) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 2d (45) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7982: not big enough for chunk (3) 2:[2] 7982: -> 0 4:[4] write_ram(40750,0) [46/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2e (46) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 2e (46) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 2e (46) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 2e (46) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 2e (46) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 2e (46) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 2e (46) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 2e (46) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7984: PHASE_CHARGE_VOLTS_LIMIT_HI -> 187 2:[2] 7985: -> 195 2:[2] 7986: -> 207 2:[2] 7987: -> 207 2:[8] 7984: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 30 (48) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 30 (48) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 30 (48) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 30 (48) [d1 ] address 0x00FF 4:[1] WRTE:4: bb (187) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: c3 (195) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: cf (207) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: cf (207) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7988: not big enough for chunk (3) 2:[2] 7988: -> 207 4:[4] write_ram(40756,207) [52/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 34 (52) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 3 (3) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 34 (52) [d2 ] 4:[1] read<5: cf (207) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 3 (3) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 34 (52) [d2 ] 4:[2] write_ram:5: cf (207) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 34 (52) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 34 (52) [d1 ] Write lo addr 4:[2] write_ram_return:4: cf (207) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 34 (52) [d1 ] Write lo addr 4:[1] read<4: cf (207) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7989: not big enough for chunk (3) 2:[2] 7989: -> 207 4:[4] write_ram(40757,207) [53/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 35 (53) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 4 (4) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 35 (53) [d2 ] 4:[1] read<5: cf (207) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 4 (4) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 35 (53) [d2 ] 4:[2] write_ram:5: cf (207) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 35 (53) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 35 (53) [d1 ] Write lo addr 4:[2] write_ram_return:4: cf (207) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 35 (53) [d1 ] Write lo addr 4:[1] read<4: cf (207) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7990: not big enough for chunk (3) 2:[2] 7990: -> 207 4:[4] write_ram(40758,207) [54/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 36 (54) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 5 (5) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 36 (54) [d2 ] 4:[1] read<5: cf (207) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 5 (5) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 36 (54) [d2 ] 4:[2] write_ram:5: cf (207) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 36 (54) [d1 ] Write lo addr 4:[1] WRTE:4: cf (207) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 36 (54) [d1 ] Write lo addr 4:[2] write_ram_return:4: cf (207) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 36 (54) [d1 ] Write lo addr 4:[1] read<4: cf (207) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 7992: PHASE_CHARGE_AMPS_LIMIT_LO -> 10 2:[2] 7993: -> 0 2:[2] 7994: -> 0 2:[2] 7995: -> 0 2:[8] 7992: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 38 (56) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 38 (56) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 38 (56) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 38 (56) [d1 ] address 0x00FF 4:[1] WRTE:4: a (10) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7996: not big enough for chunk (3) 2:[2] 7996: -> 0 4:[4] write_ram(40764,0) [60/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3c (60) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 3c (60) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 3c (60) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 3c (60) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 3c (60) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3c (60) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 3c (60) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 3c (60) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7997: not big enough for chunk (3) 2:[2] 7997: -> 0 4:[4] write_ram(40765,0) [61/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3d (61) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 3d (61) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 3d (61) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 3d (61) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 3d (61) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3d (61) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 3d (61) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 3d (61) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 7998: not big enough for chunk (3) 2:[2] 7998: -> 0 4:[4] write_ram(40766,0) [62/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3e (62) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 3e (62) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 3e (62) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 3e (62) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 3e (62) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 3e (62) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 3e (62) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 3e (62) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8000: PHASE_CHARGE_AMPS_LIMIT_HI -> 0 2:[2] 8001: -> 0 2:[2] 8002: -> 0 2:[2] 8003: -> 0 2:[8] 8000: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 40 (64) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 40 (64) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 40 (64) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 40 (64) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8004: not big enough for chunk (3) 2:[2] 8004: -> 0 4:[4] write_ram(40772,0) [68/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 44 (68) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 44 (68) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 44 (68) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 44 (68) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 44 (68) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 44 (68) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 44 (68) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 44 (68) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8005: not big enough for chunk (3) 2:[2] 8005: -> 0 4:[4] write_ram(40773,0) [69/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 45 (69) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 45 (69) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 45 (69) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 45 (69) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 45 (69) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 45 (69) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 45 (69) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 45 (69) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8006: not big enough for chunk (3) 2:[2] 8006: -> 0 4:[4] write_ram(40774,0) [70/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 46 (70) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 46 (70) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 46 (70) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 46 (70) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 46 (70) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 46 (70) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 46 (70) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 46 (70) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8008: PHASE_CHARGE_TEMP_LIMIT_LO -> 0 2:[2] 8009: -> 0 2:[2] 8010: -> 0 2:[2] 8011: -> 0 2:[8] 8008: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 48 (72) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 48 (72) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 48 (72) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 48 (72) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8012: not big enough for chunk (3) 2:[2] 8012: -> 0 4:[4] write_ram(40780,0) [76/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4c (76) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 4c (76) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 4c (76) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 4c (76) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 4c (76) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4c (76) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 4c (76) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 4c (76) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8013: not big enough for chunk (3) 2:[2] 8013: -> 0 4:[4] write_ram(40781,0) [77/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4d (77) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 4d (77) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 4d (77) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 4d (77) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 4d (77) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4d (77) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 4d (77) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 4d (77) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8014: not big enough for chunk (3) 2:[2] 8014: -> 0 4:[4] write_ram(40782,0) [78/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4e (78) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 4e (78) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 4e (78) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 4e (78) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 4e (78) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 4e (78) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 4e (78) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 4e (78) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8016: PHASE_CHARGE_TEMP_LIMIT_HI -> 0 2:[2] 8017: -> 0 2:[2] 8018: -> 0 2:[2] 8019: -> 0 2:[8] 8016: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 50 (80) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 50 (80) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: 50 (80) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: 50 (80) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 0 (0) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8020: not big enough for chunk (3) 2:[2] 8020: -> 0 4:[4] write_ram(40788,0) [84/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 54 (84) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 54 (84) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 54 (84) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 54 (84) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 54 (84) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 54 (84) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 54 (84) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 54 (84) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8021: not big enough for chunk (2) 2:[2] 8021: -> 0 4:[4] write_ram(40789,0) [85/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 55 (85) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 55 (85) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 55 (85) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 55 (85) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 55 (85) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 55 (85) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 55 (85) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 55 (85) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8022: not big enough for chunk (1) 2:[2] 8022: -> 0 4:[4] write_ram(40790,0) [86/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 56 (86) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 56 (86) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 56 (86) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 56 (86) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 56 (86) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 56 (86) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 56 (86) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 56 (86) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8032: not big enough for chunk (1) 2:[2] 8032: TURN_OFF_BALANCE_HV -> 0 4:[4] write_ram(40800,0) [96/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 60 (96) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 60 (96) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: 60 (96) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 60 (96) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: 60 (96) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: 60 (96) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: 60 (96) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: 60 (96) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8104: BALANCE_NUM_BATTERIES -> 25 2:[2] 8105: BALANCE_NUM_BATTERIES_PHASE -> 0 2:[2] 8106: BAUD_LOCKED -> 69 2:[2] 8107: BAUD -> 8 2:[8] 8104: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: a8 (168) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: a8 (168) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: a8 (168) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: a8 (168) [d1 ] address 0x00FF 4:[1] WRTE:4: 19 (25) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 45 (69) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 8 (8) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8109: not big enough for chunk (3) 2:[2] 8109: MIN_CHG_TEMP -> 100 4:[4] write_ram(40877,100) [173/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ad (173) [d1 ] Write lo addr 4:[1] WRTE:4: 64 (100) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 11 (17) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: ad (173) [d2 ] 4:[1] read<5: 64 (100) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 11 (17) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: ad (173) [d2 ] 4:[2] write_ram:5: 64 (100) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ad (173) [d1 ] Write lo addr 4:[1] WRTE:4: 64 (100) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: ad (173) [d1 ] Write lo addr 4:[2] write_ram_return:4: 64 (100) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: ad (173) [d1 ] Write lo addr 4:[1] read<4: 64 (100) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8110: not big enough for chunk (2) 2:[2] 8110: MIN_BATT_TEMP -> 0 4:[4] write_ram(40878,0) [174/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ae (174) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: ae (174) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: ae (174) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: ae (174) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: ae (174) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ae (174) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: ae (174) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: ae (174) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8111: not big enough for chunk (1) 2:[2] 8111: MIN_VOLTS -> 17 4:[4] write_ram(40879,17) [175/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: af (175) [d1 ] Write lo addr 4:[1] WRTE:4: 11 (17) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: c0 (192) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: af (175) [d2 ] 4:[1] read<5: 11 (17) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: c0 (192) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: af (175) [d2 ] 4:[2] write_ram:5: 11 (17) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: af (175) [d1 ] Write lo addr 4:[1] WRTE:4: 11 (17) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: af (175) [d1 ] Write lo addr 4:[2] write_ram_return:4: 11 (17) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: af (175) [d1 ] Write lo addr 4:[1] read<4: 11 (17) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8118: TURN_ON_BALANCE_HV -> 0 2:[2] 8119: TURN_ON_CHARGE_HV -> 155 2:[2] 8120: TURN_ON_BALANCE_PHASE -> 0 2:[2] 8121: TURN_ON_CHARGE_PHASE -> 1 2:[8] 8118: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: b6 (182) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: b6 (182) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: b6 (182) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: b6 (182) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 9b (155) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 1 (1) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8122: TURN_OFF_CHARGE_HV -> 120 2:[2] 8123: CLEAR_CHARGED_THRESH -> 153 2:[2] 8124: DIDT_WINDOW -> 100 2:[2] 8125: DIDT_UP_LIMIT -> 5 2:[8] 8122: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ba (186) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: ba (186) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: ba (186) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: ba (186) [d1 ] address 0x00FF 4:[1] WRTE:4: 78 (120) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 99 (153) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 64 (100) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 5 (5) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8126: not big enough for chunk (2) 2:[2] 8126: DIDT_CLIMB -> 1 4:[4] write_ram(40894,1) [190/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: be (190) [d1 ] Write lo addr 4:[1] WRTE:4: 1 (1) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: bf (191) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: be (190) [d2 ] 4:[1] read<5: 1 (1) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: bf (191) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: be (190) [d2 ] 4:[2] write_ram:5: 1 (1) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: be (190) [d1 ] Write lo addr 4:[1] WRTE:4: 1 (1) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: be (190) [d1 ] Write lo addr 4:[2] write_ram_return:4: 1 (1) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: be (190) [d1 ] Write lo addr 4:[1] read<4: 1 (1) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8127: not big enough for chunk (1) 2:[2] 8127: BEEP_ON_NET_TIMEOUT -> 1 4:[4] write_ram(40895,1) [191/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: bf (191) [d1 ] Write lo addr 4:[1] WRTE:4: 1 (1) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: c0 (192) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: bf (191) [d2 ] 4:[1] read<5: 1 (1) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: c0 (192) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: bf (191) [d2 ] 4:[2] write_ram:5: 1 (1) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: bf (191) [d1 ] Write lo addr 4:[1] WRTE:4: 1 (1) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: bf (191) [d1 ] Write lo addr 4:[2] write_ram_return:4: 1 (1) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: bf (191) [d1 ] Write lo addr 4:[1] read<4: 1 (1) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8162: MAX_VOLTS -> 237 2:[2] 8163: MAX_AMPS -> 150 2:[2] 8164: MAX_CHG_TEMP -> 1 2:[2] 8165: MAX_BATT_TEMP -> 160 2:[8] 8162: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: e2 (226) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: e2 (226) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: e2 (226) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: e2 (226) [d1 ] address 0x00FF 4:[1] WRTE:4: ed (237) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 96 (150) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 1 (1) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: a0 (160) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8166: PHASES_ENABLED -> 5 2:[2] 8167: SCALE_BACK_CHG_TEMP -> 49 2:[2] 8168: CHARGE_INHIBIT_ERRNO_MASK -> 0 2:[2] 8169: TIMEOUT_MINUTES -> 60 2:[8] 8166: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: e6 (230) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: e6 (230) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: e6 (230) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: e6 (230) [d1 ] address 0x00FF 4:[1] WRTE:4: 5 (5) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 31 (49) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 3c (60) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8170: not big enough for chunk (1) 2:[2] 8170: SLEEP_SECONDS -> 60 4:[4] write_ram(40938,60) [234/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ea (234) [d1 ] Write lo addr 4:[1] WRTE:4: 3c (60) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 26 (38) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: ea (234) [d2 ] 4:[1] read<5: 3c (60) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 26 (38) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: ea (234) [d2 ] 4:[2] write_ram:5: 3c (60) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: ea (234) [d1 ] Write lo addr 4:[1] WRTE:4: 3c (60) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: ea (234) [d1 ] Write lo addr 4:[2] write_ram_return:4: 3c (60) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: ea (234) [d1 ] Write lo addr 4:[1] read<4: 3c (60) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8176: not big enough for chunk (3) 2:[2] 8176: LAST_ERRNO -> 0 4:[4] write_ram(40944,0) [240/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f0 (240) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: f0 (240) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f0 (240) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: f0 (240) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f0 (240) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f0 (240) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f0 (240) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f0 (240) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8177: not big enough for chunk (3) 2:[2] 8177: -> 0 4:[4] write_ram(40945,0) [241/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f1 (241) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: f1 (241) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f1 (241) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: f1 (241) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f1 (241) [d2 ] 4:[2] write_ram:5: 0 (0) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f1 (241) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f1 (241) [d1 ] Write lo addr 4:[2] write_ram_return:4: 0 (0) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f1 (241) [d1 ] Write lo addr 4:[1] read<4: 0 (0) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8178: not big enough for chunk (3) 2:[2] 8178: PWM_SEED -> 100 4:[4] write_ram(40946,100) [242/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f2 (242) [d1 ] Write lo addr 4:[1] WRTE:4: 64 (100) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 56 (86) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f2 (242) [d2 ] 4:[1] read<5: 64 (100) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 56 (86) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f2 (242) [d2 ] 4:[2] write_ram:5: 64 (100) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f2 (242) [d1 ] Write lo addr 4:[1] WRTE:4: 64 (100) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f2 (242) [d1 ] Write lo addr 4:[2] write_ram_return:4: 64 (100) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f2 (242) [d1 ] Write lo addr 4:[1] read<4: 64 (100) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8180: not big enough for chunk (2) 2:[2] 8180: AVG_NUM -> 50 4:[4] write_ram(40948,50) [244/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f4 (244) [d1 ] Write lo addr 4:[1] WRTE:4: 32 (50) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 26 (38) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f4 (244) [d2 ] 4:[1] read<5: 32 (50) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 26 (38) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f4 (244) [d2 ] 4:[2] write_ram:5: 32 (50) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f4 (244) [d1 ] Write lo addr 4:[1] WRTE:4: 32 (50) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f4 (244) [d1 ] Write lo addr 4:[2] write_ram_return:4: 32 (50) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f4 (244) [d1 ] Write lo addr 4:[1] read<4: 32 (50) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[8] 8181: not big enough for chunk (2) 2:[2] 8181: PWM_OFFSET -> 140 4:[4] write_ram(40949,140) [245/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f5 (245) [d1 ] Write lo addr 4:[1] WRTE:4: 8c (140) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 81 (129) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f5 (245) [d2 ] 4:[1] read<5: 8c (140) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 81 (129) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f5 (245) [d2 ] 4:[2] write_ram:5: 8c (140) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f5 (245) [d1 ] Write lo addr 4:[1] WRTE:4: 8c (140) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f5 (245) [d1 ] Write lo addr 4:[2] write_ram_return:4: 8c (140) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f5 (245) [d1 ] Write lo addr 4:[1] read<4: 8c (140) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8184: DL_LOCK -> 0 2:[2] 8185: DIV_VF -> 1 2:[2] 8186: DLY_VF -> 4 2:[2] 8187: NUM_VF -> 10 2:[8] 8184: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f8 (248) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: f8 (248) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: f8 (248) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: f8 (248) [d1 ] address 0x00FF 4:[1] WRTE:4: 0 (0) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 1 (1) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 4 (4) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: a (10) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[2] 8188: NUM_SAMPLES -> 10 2:[2] 8189: LAST_MESSAGE_SIZE -> 0 2:[2] 8190: LAST_ERROR -> 0 2:[2] 8191: MY_NET_ADDR -> 1 2:[8] 8188: can output chunk 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 1f (31) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: fc (252) [d1 ] Write lo addr 4:[1] WRTE:4: 0 (0) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: fc (252) [d0 ] 4:[1] read<3: 1f (31) [d1 ] 4:[1] read<4: fc (252) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: f1 (241) [cmd ] Write block 4:[1] WRTE:2: 1f (31) [d0 ] address 0xFF00 4:[1] WRTE:3: fc (252) [d1 ] address 0x00FF 4:[1] WRTE:4: a (10) [d2 ] data byte 0 (addr) 4:[1] WRTE:5: 0 (0) [d3 ] data byte 1 (addr+1) 4:[1] WRTE:6: 0 (0) [d4 ] data byte 2 (addr+2) 4:[1] WRTE:7: 1 (1) [d5 ] data byte 3 (addr+3) 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: f3 (243) [cmd ] Write block okay 4:[1] read<2: 7c (124) [d0 ] 4:[1] read<3: 0 (0) [d1 ] 4:[1] read<4: 0 (0) [d2 ] 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[4] write_ram(40947,69) [243/159] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 3 (3) [cmd ] Prep Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f3 (243) [d1 ] Write lo addr 4:[1] WRTE:4: 45 (69) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 4 (4) [cmd ] Prep Write OK 4:[1] read<2: 38 (56) [d0 ] 4:[1] read<3: 9f (159) [d1 ] 4:[1] read<4: f3 (243) [d2 ] 4:[1] read<5: 45 (69) [d3 ] 4:[1] read<6: 7c (124) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 4:[2] write_ram:0: 1 (1) [addr ] 4:[2] write_ram:1: 4 (4) [cmd ] Prep Write OK 4:[2] write_ram:2: 38 (56) [d0 ] 4:[2] write_ram:3: 9f (159) [d1 ] 4:[2] write_ram:4: f3 (243) [d2 ] 4:[2] write_ram:5: 45 (69) [d3 ] 4:[2] write_ram:6: 7c (124) [d4 ] 4:[2] write_ram:7: 0 (0) [d5 ] 4:[1] WRTE:0: 1 (1) [addr ] 4:[1] WRTE:1: 6 (6) [cmd ] Write 4:[1] WRTE:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] WRTE:3: f3 (243) [d1 ] Write lo addr 4:[1] WRTE:4: 45 (69) [d2 ] Write Data 4:[1] WRTE:5: 0 (0) [d3 ] 4:[1] WRTE:6: 0 (0) [d4 ] 4:[1] WRTE:7: 0 (0) [d5 ] 4:[2] write_ram_return:0: 1 (1) [addr ] 4:[2] write_ram_return:1: 6 (6) [cmd ] Write 4:[2] write_ram_return:2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[2] write_ram_return:3: f3 (243) [d1 ] Write lo addr 4:[2] write_ram_return:4: 45 (69) [d2 ] Write Data 4:[2] write_ram_return:5: 0 (0) [d3 ] 4:[2] write_ram_return:6: 0 (0) [d4 ] 4:[2] write_ram_return:7: 0 (0) [d5 ] 4:[1] read<0: 1 (1) [addr ] 4:[1] read<1: 7 (7) [cmd ] Write OK 4:[1] read<2: 9f (159) [d0 ] Write hi addr +0x80 for ee 4:[1] read<3: f3 (243) [d1 ] Write lo addr 4:[1] read<4: 45 (69) [d2 ] Write Data 4:[1] read<5: 0 (0) [d3 ] 4:[1] read<6: 0 (0) [d4 ] 4:[1] read<7: 0 (0) [d5 ] 2:[1] Written: 129 bytes (21 chunks 45 singles) wtih 0 errors